5. Februar 2016
Why Hidden Pins are Evil (and Nets Should Only Have One Name)

Since some years ago I use the KiCad EDA suite. (And I also collaborated on the translation of the KiCad documentation.)

I’m a electronics engineer and hardware developer in a big company where I do embedded designs in high voltage environments.

KiCad makes a lot of things right but there are some things that annoy me. One is the „one net multiple names“ „feature“ which is made worse by an even more annoying „feature“: hidden pins.

Sadly I can’t separate those two features from another because one has influence on the other. Therefore this long text, here you go:

Why Hidden Pins?

One argument behind hidden pins is, that it makes designing a circuit less cluttered. You just name your power supply „VDD“ and are done. No wires to draw and all your (digital) components are powered.

But let’s face it: modern designs need multiple voltage rails, one single rail is not enough today (if it was ever). Only the simplest circuits work with one single voltage.

In real applications this „feature“ causes more problems than it solves.

In a real world application you need decoupling capacitors close to your components. Where do you draw them in your schematic design? Close to your components? Anywhere else on your sheet? You need to draw the supply wires anyway.

Another argument is that you need to hide them when using the same symbol for all gates of a multi-part component.

I think that can be fixed if you choose to have multiple symbols for a multi-part comonent, e.g. 4 logic gates and 1 power gate for a 7400, or a amplifier symbol with and one symbol without supply pins for a dual op-amp. (In our company it is implemented exactly this way.)

Real World Concequences

I made a design spanning 5 hierarchical sheets in an older version of KiCad. There the hidden pins were handled different than in recent versions of KiCad: When you made the hidden pins on a component visible they did not connect anymore to the other – still hidden – pins. They only connected to an explicitly drawn wire connected to that pin.

The recent versions of KiCad ignore this behaviour and connect the now visible pin also to the still hidden pins. What’s even more evil about this: they connect to a net that has the same name as the pin on the device which itself is connected to a different named net. KiCad therefore connects two nets with different names. And this is not obvious to the user and KiCad shows no warning about this. (Only if you study the documentation you have a chance to find a hint about this.)

In my application I used a component provided by a KiCad library. It had hidden pins. I made them visible and connected them to a net ‚+5V‘. On another sheet in my design I had a power net named ‚VDD‘ that I only used on that sheet. But power nets are global nets. So KiCad silently connected ‚+5V‘ and ‚VDD‘. And because KiCad allows multiple names on the same net the ERC does not throw an error.

It only occurred to me because it was an existing design and in the PCB design tool Pcbnew there was a ratsnest wire where none should be. What if this was a fresh design? I would probably have ended with a board where two nets – that I wanted to be separate – would be connected.

Nobody can have that in a professional design.

Working in a Professional Environment

In a professional environment design reviews are state of the art. This is true for hardware and software projects. The review is usually done by experts that are not part of the actual project team („outsiders“) to ensure that approved design rules are applied and of course that the design is correct and robust.

In my company there are complex schematic designs that span up to 60 sheets and may contain more than 1300 components. Those are maintained by up to 5 developers at a given time and are partly derived from former designs. Most designs see one or more redesigns due to changed requirements or necessary modifications found during testing. So you have a mix of many different people who work over a long period of time on a complex schematic.

How do you want to be able to check a (complex) schematic for its correctness when there are connections that are not visible in the schematic? How do you check if that one IC is connected to the right power rail(s) and if it is correctly buffered when the supply net is not displayed in the schematic? How do you want to (safely) derive a work from such a design?

When our schematics are reviewed and finished they go to the PCB design department or even to an external PCB design service. How should they know how to place the parts? Do you really want to assist them on each part? A clean and descriptive schematic is the key to a fast PCB design realization. (Yes there are PCB design reviews as well but this approach reduces the modifications to only special cases.)

Display All The Pins

Each device has at least conductive connections (a.k.a. pins) but may also have not-connected conductive pins (for mounting purposes), non-conductive pins, holes for mounting that need plated holes etc. They should all be visible in the schematic. The schematic is the place where you can add comments (texts) on those pins, to describe what’s their purpose. You can’t do that in the PCB design.

Also it may be desired to bind those (electrical) unused pins to a potential, e.g. Ground or Protected Earth. Those pins also influence your insulation distances when you have a design that must handle high voltages. Mounting holes may shorten your creepage distance between different potential nets on your board.

Lets say you have a device with 16 actual pins but only 10 of them are active. You now design your schematic symbol with only the 10 active pins. You may be surprised when going into the PCB design and the actual component takes the space of a 16 pin device.

All of those pins ignored in the schematic are there on the PCB and block your routing path…

There Can Be Only One

Let’s look on the „feature“ „one net – multiple names“.


„The schematic is for a hardware design what the source code is for a software project.“

  • Both define the behaviour of the final design (hardware vs. software).
  • Both can/should/must have comments for better understanding of the design or design decisions.


„Wires in a hardware design are like variables in a software design.“

  • Both must have a name for access in the design.
  • Both connect two or more places in the design.
  • Both may have multiple names for easier access. But: is it really a good idea?

I expect you also don’t want hidden features in your software framework that connects one of your variables somehow to some other variable of your code. So why should this be a good idea in a hardware design?


Remove the „hidden pin“ feature completely

For professional use this simply is a „no go“. Also I would expect removing this also removes complexity from the KiCad source code. Yes it breaks old designs. But in my opinion using this feature makes them broken by design anyway.

Settle for a „one net – one name“ policy

If it is really such a requirement and widely used – transform it to „net aliases“ but let KiCad have a way to check for different labels on the same net. Old (and new) designs would get a warning or error during ERC and then could automatically/assisted rename the multiple net-labels to „net aliases“.

What’s your take on those issues? Place your opinion in the comments below!

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